1. Field of the Invention
The present invention relates to a nonvolatile memory. More particularly, the present invention relates to a nonvolatile memory, on which electrical write and electrical erase can be performed (electrically erasable and programmable read only memory: EEPROM) and may include an EEPROM, on which electrical erase can be performed for every one bit and a flash memory.
2. Description of the Related Art
Memories may be mainly divided into two categories of volatile memories and nonvolatile memories. Typical types of volatile memories may be static random access memories (SRAM) and dynamic random access memories (DRAM). Typical types of nonvolatile memories may be EEPROM, flash EEPROM and magnetic disk. The volatile memory such as SRAM and DRAM has a drawback that data to be used is temporally stored but the data is lost when powered off. On the other hand, the nonvolatile memory such as EEPROM, flash EEPROM and magnetic disks does not lose the data even when powered off and may be used for storing a program for system start.
The nonvolatile memory such as EEPROM and flash EEPROM has a better to characteristic in scale of integration, shock-proof, power consumption, write/read speed and so on than those of magnetic disks. As a result, EEPROM and flash EEPROM may be used as alternatives of magnetic disks or the nonvolatile memories.
Especially, the scale of integration of EEPROM has been improved double for one year and is still being developed at a very fast pace. Thus, mass production of the EEPROM having some giga-bit of capacity can be expected in near future and will go beyond DRAM in scale of integration. Technologies supporting the improvement in scale of integration may include the improvement of circuit configurations, microfabrication technologies and multilevel technologies.
Among those technologies, the multilevel technologies have gathered attentions in recent years, which hold three or more values of data in one memory cell. The multilevel technologies control the amount of charges, which are accumulated in a charge-accumulated area, and discriminate three or more different states of the memory cell. In practice, quaternary flash memory is commercialized, which can distinguish four different states of the memory cell.
Now, an example of a typical circuit in a memory cell array (MCA) of an electrically programmable and electrically erasable nonvolatile memory, such as EEPROM and flash EEPROM, will be described with reference to FIG. 13.
A memory cell array 401 has m word lines (WL1 to WLm), n bit lines (BL1 to BLn), and multiple memory cells 400 arranged in a matrix manner. Each of the memory cells 400 has a memory transistor 404. The memory transistor 404 has a floating gate, a control gate, a source region and a drain region. The control gate of the memory transistor 404 is connected to any one of the word lines (WL1 to WLm). Either the source region or the drain region of the memory transistor 404 is connected to any one of bit lines (BL1 to BLn). The other is connected to a common electrode (SC). A bit line side drive circuit 402, a word line side drive circuit 403, a write/erase circuit 406a and a read circuit 406b are provided around the memory cell array 401.
FIGS. 14A to 14C schematically show sectional views of the memory transistor 404 shown in FIG. 13. Each of FIGS. 14A to 14C includes a floating gate (FG) 1, a control gate (CG) 2, a substrate 3, a source region (S) 4 and a drain region (D) 5. “e−” in FIGS. 14A to 14C indicates an electron implanted to the floating gate (FG) 1. The substrate 3 is a silicon substrate to which an impurity element is added to the source region 4 and the drain region 5. Further, one conductive type is given thereto. Here, the polarity of the source region 4 and the drain region 5 is the n-type and the polarity of the substrate 3 is the p-type.
Now, a case where electrical write is performed on the memory cell 400 having binary information will be described with reference to FIG. 14B. A case where the information is electrically read out from the memory cell 400 will be described with reference to FIGS. 14C and 15A.
First of all, the electrical write on the memory cell 400 will be described with reference to FIG. 14B. It is assumed that a voltage Vg (for example, 12V, here) is applied to the control gate (CG) 2. A voltage Vd (for example, 6V, here) is applied to the drain region 5. The ground voltage (0 V) is applied to the source region 4. Then, the memory cell 400 is turned ON, and electrons flow from the source region 4 to the drain region 5 in the memory cell 400. Applying voltages (signal voltages) to the control gate (CG) 2, the source region 4 and the drain region 5 is called biasing herein.
Then, parts of electrons, which are accelerated in a pinch-off region (not shown) near the drain region 5, become channel hot electrons (CHE), which are captured by the floating gate (FG) 1. In other words, parts of electrons which become hot electrons (HE) are accumulated in the floating gate (FG) 1. An amount of electrons accumulated in the floating gate (FG) 1 is determined by three factors including a threshold voltage before biased, voltages applied to the control gate (CG) 2, the source region 4 and the drain region 5 of the memory transistor when biased, and a time when the voltages are applied.
When electrons are implanted to the floating gate (FG) 1, the threshold voltage of the memory cell 400 is increased. Which information between “0” and “1” the memory cell 400 has is determined based on the threshold voltage of the memory cell 400.
Next, electrical read performed on the memory cell 400 will be described with reference to FIGS. 14C and 15A.
FIG. 15A shows distributions of threshold voltages of the memory cell 400 (having information “1”) in which electrons are implanted to the floating gate (FG) 1 and the memory cell 400 (having information “0”) in which electrons are not implanted to the floating gate (FG) 1. In each of FIGS. 15A and 15B, the vertical axis indicates the threshold voltages and the horizontal axis indicates the number (the bit number) of memory cells 400 in the memory cell array 401.
As shown in FIG. 15A, the memory cell 400 having a threshold voltage of 5.0 V or higher has information “1”. The memory cell 400 having a threshold lower than 5.0 V has information “0”. By referring the threshold voltage 5.0 V, which information “1” or “0” the memory cell 400 has is determined. The threshold voltage is called reference voltage herein.
Now, as one example shown in FIG. 14C, a voltage Vg (for example, 5 V here) is applied to the control gate (CG) 2 and a voltage Vd (for example, 2V here) is applied to the drain region 5. Further, a ground potential (for example, 0 V here) is applied to the source region 4 of the memory cell 400. Under the condition, the electrical read is performed.
It is assumed that the memory cell 400 having information “0” is biased under the condition as shown in FIG. 14C. Then, the memory cell 400 is turned ON, where current flows.
On the other hand, the memory cell 400 having information “1” is biased under the condition as shown in FIG. 14C. In this case, charges are accumulated in the floating gate (FG) 1, and the threshold voltage is increased. As a result, the memory cell 400 remains in the OFF state, where current does not flow. Which information “0” or “1” the memory cell 400 has can be determined by detecting the presence of the current.
Next, the multilevel technology whereby more information can be written in one memory cell 400 by adjusting an amount of charges accumulated in the floating gate (FG) 1 will be described with reference to FIGS. 16A and 16B. FIGS. 16A and 16B shows distribution of threshold voltages of the memory cells 400 in which write is performed by using the multi-level technology.
Here, amounts of charges accumulated in the memory cell 400 are indicated by a, b, c and d, respectively. It is assumed that the proportional relationship among them is a>b>c>d. FIGS. 16A and 16B include distributions A, B, C and D. The distribution A is no a distribution of threshold voltage of the memory cell 400 when the amount of charges accumulated in the memory cell 400 is a (having information “0”). The distribution B is a distribution of threshold voltage of the memory cell 400 when the amount of charges accumulated in the memory cell 400 is b (having information “1”). The distribution C is a distribution of threshold voltage of the memory cell 400 when the amount of charges accumulated in the memory cell 400 is c (having information “2”). The distribution D is a distribution of threshold voltage of the memory cell 400 when the amount of charges accumulated in the memory cell 400 is d (having information “3”).
Then, the threshold voltage distribution A ranges 0.5 V to 1.5 V. The threshold voltage distribution B ranges 1.5 V to 3.0 V. The threshold voltage distribution C ranges 3.0 V to 4.5 V. The threshold voltage distribution D ranges 4.5 V or higher. Here, three voltages of 1.5 V, 3.0 V and 4.5 V are reference voltages. An operation of the multi-level nonvolatile memory will be omitted here since it is similar to the operation of the binary nonvolatile memory.
According to the multilevel technology, the threshold voltages of the memory cells 400 are controlled such that more information can be stored in one memory cell 400, as described above.
By the way, the binary or multi-level nonvolatile memory undergoes verify operations (verify write and verify erase) for verifying that the threshold voltage of a memory transistor is within a predetermined range during an electrical write operation and electrical erase operation. Especially, an amount of electrons accumulated in the memory transistor must be controlled with high precision in the multi-level nonvolatile memory. Thus, the verify operations are necessary.
The verify operation is an operation for alternately performing a write/erase period and a read period for verifying that a state after the write/erase is within a predetermined range. Here, the verify operation will be described with reference to FIGS. 17A and 17B.
FIG. 17A shows a memory cell 400, a read circuit 406a and a write/erase circuit 406b. In FIG. 17A, the read circuit 406a and the write/erase circuit 406b are connected to the memory cell 400 located at a coordinate (x, y). Verify signals (Sv) are output from the read circuit 406a, and the verify signals (Sv) are input to the write/erase circuit 406b. The write/erase circuit 406b performs write/erase on the memory cell 400 by referencing the verify signals (Sv).
Next, the electrical write operation and the electrical erase operation in the verify operation will be described with reference to FIG. 17B. First of all, the read circuit 406a is activated (indicated as “active”) and the electrical read operation is performed. Here, the write/erase circuit 406b does not operate (indicated as “not active”). The verify signals (Sv) output from the read circuit 406a become Low signals when the state of the read memory cell 400 is different from an intended state. When the state of the read memory cell 400 is the same as the intended state, the verify signals (Sv) become High signals.
When the verify signals (Sv) are Low signals, the write/erase circuit 406b is activated (active) after the electrical read operation ends, and write/erase is performed for a certain period of time. Next, the electrical read operation is performed again and the state of the memory cell 400 is compared with the intended state. Similarly, when the verify signals (Sv) are Low signals, write/erase is performed again for a certain period of time. These operations are repeated and end when the verify signals (Sv) are High signals. The operation is called verify operation.
When electrons are implanted in the memory cell 400 and is left as is after the threshold voltage is increased to a predetermined value, a shift phenomenon occurs where the threshold voltage of the memory cell 400 is decreased with the passage of time. The shift phenomenon occurs because electrons having been accumulated in the floating gate (FG) 1 of the memory cell 400 are released from the floating gate (FG) 1 with the passage of time.
Now, the shift phenomenon will be described with reference to FIGS. 15A to 16B.
FIG. 15A shows distributions of threshold voltages of a memory cell array immediately after electrons are implanted to a memory cell of a binary nonvolatile memory. FIG. 15B shows distributions of threshold voltages of the memory cell array after a lapse of a certain period of time. FIG. 16A shows distributions of threshold voltages of a memory cell array immediately after electrons are implanted to a memory cell of a quaternary nonvolatile memory. FIG. 16B shows distributions of threshold voltages of the memory cell array after a lapse of a certain period of time.
The binary nonvolatile memory shown in FIG. 15B has sufficient margins for in the distributions of the threshold voltages (a difference between distributions of threshold voltages). Therefore, the small reduction of the threshold voltages seems not to effect on electrical read of information very much. However, it is difficult to take margins sufficiently because the supply voltage has been reduced in the binary nonvolatile memory.
In the multi-level nonvolatile memory shown in FIG. 16B, the margin between distributions of threshold voltages is very small. Thus, the decrease in distributions of threshold voltages due to a shift phenomenon cannot be ignored. As shown in FIG. 16B, an area shaded by dashed lines in the distributions C and D has information “2” and “3”, respectively. However, due to the shift phenomenon, these areas belong to distribution areas of the threshold voltages having information “1” and “2”, respectively. When electrical read is performed under this condition, stored information is converted to different information. As a result, data destruction occurs.
The shift phenomenon may be caused not only by a cause with a passage of time but also by reading stress. The reading stress is a phenomenon that electrons are released due to the voltage applied to a memory cell from the floating gate (FG) 1 of a memory cell in the same row or in the same column as that of the memory cell to which the voltage is applied during the electrical read operation.